UPSD3212BV-40U1(2009) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

UPSD3212BV-40U1
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

UPSD3212A, UPSD3212C, UPSD3212CV

UPSD321xx hardware description

3

UPSD321xx hardware description

The UPSD321xx devices have a modular architecture with two main functional modules: the

MCU module and the PSD module. The MCU module consists of a standard 8032 core,

peripherals and other system supporting functions. The PSD module provides configurable

Program and Data memories to the 8032 CPU core. In addition, it has its own set of I/O

ports and a PLD with 16 macrocells for general logic implementation. Ports A,B,C, and D

are general purpose programmable I/O ports that have a port architecture which is different

from Ports 0-4 in the MCU module.

The PSD module communicates with the CPU Core through the internal address, data bus

(A0-A15, D0-D7) and control signals (RD_, WR_, PSEN_ , ALE, RESET_). The user

defines the Decoding PLD in the PSDsoft Development Tool and can map the resources in

the PSD module to any program or data address space.

Figure 14. UPSD321xx functional modules

Port 3, UART,

Intr, Timers,I2C

Port 1, Timers and

2nd UART and ADC

Port 4 PWM

Dedicated

USB Pins

Port 3

Port 1

8032 Core

I2C

2 UARTs

Interrupt

3 Timer /

Counters

256 Byte SRAM

4

Channel

ADC

PWM

5

Channels

USB

&

Transceiver

Reset Logic

LVD & WDT

MCU MODULE

PSD MODULE

Page Register

Decode PLD

8032 Internal Bus

A0-A15

RD,PSEN

WR,ALE

Port 0, 2

Ext. Bus

D0-D7 Reset

512Kb

Main Flash

128Kb

Secondary

Flash

16Kb

SRAM

Bus

Interface

PSD Internal Bus

JTAG ISP

CPLD - 16 MACROCELLS

VCC, GND,

XTAL

Port C,

JTAG, PLD I/O

and GPIO

Port A & B, PLD

I/O and GPIO

Port D

GPIO

Dedicated

Pins

AI07426b

35/181

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