Interrupt system
Figure 15. Interrupt system
Interrupt
IE /
Sources
INT0
USART
Timer
0
I2C
INT1
UPSD3212A, UPSD3212C, UPSD3212CV
IP / IPA Priority
High
Low
Timer
1
USB
2nd
USART
Timer
2
Global
Enable
AI07427b
Table 18. SFR register description
SFR
Add
r
Reg
Name
7
Bit Register Name
6
5
4
3
2
A7 IEA
—
—
—
ES2
—
—
A8 IE
EA
B7 IPA
—
—
ET2 ES
ET1 EX1
—
—
PS2
—
—
B8 IP
—
—
PT2 PS
PT1 PX1
1
EI2C
ET0
PI2C
PT0
Rese
0
t
Valu
Comments
e
Interrupt
EUSB 00 Enable
(2nd)
EX0
00
Interrupt
Enable
Interrupt
PUSB 00 Priority
(2nd)
PX0
00
Interrupt
Priority
5.8
Interrupt priority structure
Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are
defined by the interrupt priority special function register IP and IPA.
0 = low priority
1 = high priority
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