UPSD3212A, UPSD3212C, UPSD3212CV
Watchdog timer
Figure 20. RESET pulse width
Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz)
Reset period
(1.258 second at 40Mhz)
(about 6.291 seconds at 8Mhz)
AI06823
Table 34.
7
Reserved
Watchdog timer clear register (WDRST: 0A6h)
6
5
4
3
2
WDRST6 WDRST5 WDRST4 WDRST3 WDRST2
1
WDRST1
0
WDRST0
Table 35.
Bit
7
6 to 0
Description of the WDRST Bits
Symbol
Function
—
Reserved
WDRST6
to
WDRST0
To reset watchdog timer, write any value beteen 00h and 7Eh to this
register.
This value is loaded to the 7 most significant bits of the 22-bit counter.
For example: MOV WDRST,#1EH
1. The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled.
57/181