UPSD3212A-40U6(2009) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
UPSD3212A-40U6
(Rev.:2009)
(Rev.:2009)
STMicroelectronics
UPSD3212A-40U6 Datasheet PDF : 181 Pages
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UPSD3212A, UPSD3212C, UPSD3212CV
USB hardware
Table 61. Description of the UADR Bits
Bit
Symbol
R/W
Function
7
USBEN
6 to 0
UADD6 to
UADD0
USB Function Enable Bit.
R/W
When USBEN is clear, the USB module will not respond to
any tokens from host.
RESET clears this bit.
Specify the USB address of the device.
R/W
RESET clears these bits.
Table 62. USB interrupt enable register (UIEN: 0E9h)
7
6
5
4
3
2
SUSPNDI RSTE RSTFIE TXD0IE RXD0IE TXD1IE
1
EOPIE
0
RESUMI
Table 63.
Bit
7
6
5
4
3
2
1
0
Description of the UIEN bits
Symbol
R/W
Function
SUSPNDI R/W Enable SUSPND Interrupt
RSTE
R/W
Enable USB Reset; also resets the CPU and PSD modules
when bit is set to '1.'
RSTFIE
R/W Enable RSTF (USB Bus Reset Flag) Interrupt
TXD0IE
RXD0IE
R/W Enable TXD0 Interrupt
R/W Enable RXD0 Interrupt
TXD1IE
R/W Enable TXD1 Interrupt
EOPIE
R/W Enable EOP Interrupt
RESUMI
R/W Enable USB Resume Interrupt when it is the Suspend mode
Table 64.
7
SUSPND
USB interrupt status register (UISTA: 0E8h)
6
5
4
3
2
—
RSTF
TXD0F RXD0F TXD1F
1
EOPF
0
RESUMF
Table 65.
Bit
7
6
5
Description of the UISTA bits
Symbol
R/W
Function
SUSPND
USB Suspend Mode Flag.
To save power, this bit should be set if a 3ms constant idle
R/W state is detected on USB bus. Setting this bit stops the clock to
the USB and causes the USB module to enter Suspend mode.
Software must clear this bit after the Resume flag (RESUMF)
is set while this Resume Interrupt Flag is serviced
—
RSTF
—
Reserved
USB Reset Flag.
This bit is set when a valid RESET signal state is detected on
R
the D+ and D- lines. When the RSTE bit in the UIEN Register
is set, this reset detection will also generate an internal reset
signal to reset the CPU and other peripherals including the
USB module.
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