UPSD3212C-40U6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

UPSD3212C-40U6

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

uPSD3212A, uPSD3212C, uPSD3212CV

Decode PLD (DPLD)

The DPLD, shown in Figure 55, is used for decod-

ing the address for PSD MODULE and external

components. The DPLD can be used to generate

the following decode signals:

– 4 Sector Select (FS0-FS3) signals for the

primary Flash memory (three product terms

each)

– 2 Sector Select (CSBOOT0-CSBOOT1)

signals for the secondary Flash memory (three

product terms each)

– 1 internal SRAM Select (RS0) signal (two

product terms)

– 1 internal CSIOP Select signal (selects the

PSD MODULE registers)

– 2 internal Peripheral Select signals

(Peripheral I/O Mode).

Figure 55. DPLD Logic Array

3

CSBOOT 0

3

CSBOOT 1

I /O PORTS (PORT A,B,C)1

(INPUTS)

(20)

MCELLAB.FB [7:0] (FEEDBACKS) (8)

MCELLBC.FB [7:0] (FEEDBACKS) (8)

PGR0 - PGR7

(8)

A[15:0]2

(16)

PD[2:1]

(2)

PDN (APD OUTPUT)

(1)

PSEN, RD, WR, ALE2

(4)

RESET 2

(1)

RD_BSY

(1)

Note: 1. Port A inputs are not available in the 52-pin package

2. Inputs from the MCU module

3

FS0

3

FS1 4 PRIMARY FLASH

MEMORY SECTOR

3

FS2 SELECTS

3

FS3

2

RS0

SRAM SELECT

1

CSIOP

I/O DECODER

SELECT

1

PSEL0

PERIPHERAL I/O

1

PSEL1

MODE SELECT

AI07436

108/163

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