UPSD3212C-40U6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

UPSD3212C-40U6

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

uPSD3212A, uPSD3212C, uPSD3212CV

Address Register (S2ADR)

This 8-bit register may be loaded with the 7-bit

slave address to which the controller will respond

when programmed as a slave receive/transmitter.

The Start/Stop Hold Time Detection and System

Clock registers (Tables 57 and 58) are included in

the I2C unit to specify the start/stop detection time

to work with the large range of MCU frequency val-

ues supported. For example, with a system clock

of 40MHz.

Table 56. Address Register (S2ADR)

7

6

5

4

3

2

1

0

SLA6

SLA5

SLA4

SLA3

SLA2

SLA1

SLA0

—

Note: SLA6 to SLA0: Own slave address.

Table 57. Start /Stop Hold Time Detection Register (S2SETUP)

Address Register Name Reset Value

Note

SFR D2h

S2SETUP

00h

To control the start/stop hold time detection for the multi-master

I²C module in Slave Mode

Table 58. System Cock of 40MHz

S1SETUP,

Number of Sample

S2SETUP Register Clock (fOSC/2 – >

Value

50ns)

00h

1EA

80h

1EA

81h

2EA

82h

3EA

...

...

8Bh

12EA

...

...

FFh

128EA

Required Start/

Stop Hold Time

Note

50ns

50ns

100ns

150ns

...

600ns

...

6000ns

When Bit 7 (enable bit) = 0, the number of

sample clock is 1EA (ignore Bit 6 to Bit 0)

Fast Mode I²C Start/Stop hold time specification

Table 59. System Clock Setup Examples

System Clock

S1SETUP,

S2SETUP Register

Value

40MHz (fOSC/2 – > 50ns)

8Bh

30MHz (fOSC/2 – > 66.6ns)

89h

20MHz (fOSC/2 – > 100ns)

86h

8MHz (fOSC/2 – > 250ns)

83h

Number of Sample

Clock

Required Start/Stop Hold Time

12 EA

9 EA

6 EA

3 EA

600ns

600ns

600ns

750ns

75/163

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