M27W801-150N6TR(2006) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M27W801-150N6TR Datasheet PDF : 16 Pages
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Device operation
2
Device operation
M27W801
The operating modes of the M27W801 are listed in the Operating Modes table. A single
power supply is required in the read mode. All inputs are TTL levels except for GVPP and
12V on A9 for Electronic Signature and Margin Mode Set or Reset.
2.1
Read mode
The M27W801 has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E) is the power control and should be used for
device selection. Output Enable (G) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is
available at the output after a delay of tGLQV from the falling edge of G, assuming that E has
been low and the addresses have been stable for at least tAVQV-tGLQV.
2.2
Standby mode
The M27W801 has a standby mode which reduces the supply current from 15mA to 20µA
with low voltage operation VCC ≤3.6V, see Read Mode DC Characteristics table for details.
The M27W801 is placed in the standby mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are in a high impedance state, independent of
the GVPP input.
2.3
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, the product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
● the lowest possible memory power dissipation
● complete assurance that output bus contention will not occur
For the most efficient use of these two control lines, E should be decoded and used as the
primary device selecting function, while G should be made a common connection to all
devices in the array and connected to the READ line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
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