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TDA9106 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
TDA9106 Datasheet PDF : 30 Pages
First Prev 21 22 23 24 25 26 27 28 29 30
OPERATING DESCRIPTION (continued)
Figure 12 : LOCK/UNLOCK Block Diagram
TDA9106
5V
From
Phase
Comparator
A
NOR1
20kH-Lock CAP
B
13
220nF
6.5V
6V
37 HLOCKOUT
When PLL1 is unlocked, the 100ns negative pulse
on A becomes much larger and consequently the
average level on Pin 13 decreases. It forces Hlock-
out to go high.
The Pin 13 status is approximately the following :
- near 0V when there is no H-Sync
- between 0 and 4V with H-Sync frequency differ-
ent from VCO
- between 4 to 8 V when VCO frequency reaches
H-Sync one (but not already in phase)
- near 8V when PLL1 is locked.
It is important to notice that Pin 13 is not an
output pin but is only used for filtering purpose
(see Figure 12).
The lock/unlock information is also available throw
I2C read.
The phase comparator of PLL2 (phase type com-
parator) is followed by a charge pump with ± 0.5mA
(typ.) output current.
The flyback input is composed of an NPN transis-
tor. This input must be current driven. The maxi-
mum recommanded input current is 2mA
(see Figure 14).
Figure 14 : Flyback Input Electrical Diagram
HFLY 6
400
Q1
20k
GND 0V
II.3 - PLL2
The PLL2 ensures a constant position of the
shaped flyback signal in comparion with the saw-
tooth of the VCO (Figure 13).
Figure 13 : PLL2 Timing Diagram
H Osc
Sawtooth 7/8TH
1/8TH
6.4V
4.0V
1.6V
Flyback
Internally
Shaped Flyback
H Drive
Ts
Duty Cycle
The duty cycle of H-drive is adjustable between 30% and 60%.
The duty cycle is adjustable through I2C from 30%
to 60%. For Start Up safe operation, initial duty
cycle (after Power on reset) is 60% so as to avoid
too long conduction of BU transistor.
Maximum storage time is about 43.75% - (Tfly/2.TH).
Typically, Tfly/TH is around20% thatmeansTs max is
around 33.75%.
II.4 - Output Section
The H-drive signal is transmitted to the output
through a shaping block ensuring Ts and I2C ad-
justable duty cycle. In order to secure scanning
power part operation, the output is inhibited in the
following circumstances :
- VCC too low
- Xray protection activated
- During horizontal flyback
- I2C bit control (voluntary inhibition by MCU).
The output stage is composedof a NPN Darlington
bipolar transistor. Both the collector and the emittor
are accessible (see Figure 16).
Theoutput Darlington is in off-statewhen the power
scanning transistor is also in off-state.
21/30

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