DSPIC33FJ32GS610-50I/PT View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ32GS610-50I/PT
Microchip Technology
DSPIC33FJ32GS610-50I/PT Datasheet PDF : 456 Pages
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.3 Special MCU Features
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 features a 17-bit
by 17-bit single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can per-
form signed, unsigned and mixed sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 supports 16/16
and 32/16 divide operations, both fractional and inte-
ger. All divide instructions are iterative operations. They
must be executed within a REPEAT loop, resulting in a
total execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CPU
CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
Interrupt
Controller
X Data Bus
8
16
16
16
16
Data Latch Data Latch
23
23
PCU PCH PCL
Program Counter
X RAM
Y RAM
16
Stack
Control
Logic
Loop
Control
Logic
Address
Latch
Address
Latch
23
16
16
Address Latch
Address Generator Units
Program Memory
Data Latch
24
Instruction
Decode and
Control
Control Signals
to Various Blocks
ROM Latch
EA MUX
16 16
Instruction Reg
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
DS70591E-page 34
2009-2012 Microchip Technology Inc.
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