CDB8952T-IQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CDB8952T-IQ

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Cirrus Logic 

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

COL is not synchronous to RX_CLK. It may tran-

sition at any time.

False Carrier Detection

A false carrier condition is detected when the re-

ceiver has asserted CRS but a valid /J/K code group

sequence is not received.

When this condition is detected, the CS8952T will

assert RX_ER and place 1110 on the RXD[3:0]

pins until either the receiver detects at least two

consecutive IDLE code groups. In addition, the

False Carrier Count Register (address 13h) will be

incremented.

100 Mb/s Loopback

The CS8952T includes two 100 Mb/s loopback

modes.

Local loopback redirects the TXD[3:0] input data

to RXD[3:0] data outputs through the 4B5B coders

and scramblers. Local loopback is selected by as-

serting pin LPBK, by setting the LPBK bit (bit 14)

in the Basic Mode Control Register (address 00h)

or by setting bits 8 and 11 in the Loopback, Bypass,

and Receiver Error Mask Register (address 18h) as

shown in Table 4.

Remote loopback redirects the analog line interface

inputs to the analog line driver outputs. Remote

loopback is selected by setting bit 9 in the Loop-

back, Bypass, and Receiver Error Mask Register

(address 18h) as shown in Table 4.

Remote PMD

Loopback Loopback

(bit 9) (bit 8)

Function

0

0 No Loopback

0

1 Local Loopback (toward MII)

1

0 Remote Loopback (toward

line)

1

1 Operation is undefined

Table 4. Loopback Mode Selection

When changing between local and non-loopback

modes, the data on RXD[3:0] will be undefined for

approximately 330 µs.

100BASE-X Symbol Modes

The CS8952T provides two low latency modes for

100BASE-X repeater applications. These are se-

lected by asserting either pin BPALIGN or

BP4B5B. Both pins have the effect of bypassing

the 4B5B encoder and decoder. Bypassing the cod-

ers decreases latency, and uses a 5-bit wide parallel

code group interface on pins RXD[4:0] and

TXD[4:0] instead of the 4-bit wide MII nibble in-

terface on pins RXD[3:0] and TXD[3:0]. In repeat-

er mode, pin RX_ER is redefined as the fifth

receive data bit (RXD4), and pin TX_ER is rede-

fined as the fifth transmit data bit (TXD4).

BPALIGN can also be selected by setting bit 12 in

Loopback, Bypass, and Receiver Error Mask Reg-

ister (address 18h). BP4B5B can be selected by set-

ting bit 14 of the same register.

Pin BPALIGN causes more of the CS8952T to be

bypassed than the BP4B5B pin. BPALIGN also

bypasses the scrambler/descrambler (see Figure 1).

Asserting the REPEATER pin or setting bit 12 in

the PCS Sublayer Configuration Register (address

17h) redefines the function of the CRS (carrier

sense) pin to be asserted only on receive activity.

The REPEATER pin is also used to enable the Car-

rier Integrity Monitor feature by default.

For repeater applications, the RX_EN pin can be

used to gate the receive data pins (RXD[4:0],

RX_CLK, RX_DV, COL, and CRS) onto a shared,

external repeater system bus.

Carrier Integrity Monitor

The Carrier Integrity Monitor function allows a re-

peater to protect the attached network from some

transient fault conditions that would disrupt net-

work communications. The CS8952T contains a

self-interrupt capability to prevent a segment’s

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

20

DS206TPP2

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