C8051F521A-IM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F521A-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

SFR Definition 14.1. OSCICN: Internal Oscillator Control

R/W

R/W

R/W

R

R

R/W

R/W

R/W

Reset Value

IOSCEN1 IOSCEN0 SUSPEND IFRDY

—

IFCN2 IFCN1 IFCN0 11000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xB2

Bits7–6: IOSCEN[1:0]: Internal Oscillator Enable Bits.

00: Oscillator Disabled.

01: Reserved.

10: Reserved.

11: Oscillator Enabled in Normal Mode and Disabled in Suspend Mode.

Bit5: SUSPEND: Internal Oscillator Suspend Enable Bit.

Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The internal oscil-

lator resumes operation when one of the SUSPEND mode awakening events occur.

Bit4: IFRDY: Internal Oscillator Frequency Ready Flag.

0: Internal Oscillator is not running at programmed frequency.

1: Internal Oscillator is running at programmed frequency.

Bit3: UNUSED. Read = 0b, Write = don't care.

Bits2–0: IFCN2–0: Internal Oscillator Frequency Control Bits.

000: SYSCLK derived from Internal Oscillator divided by 128 (default).

001: SYSCLK derived from Internal Oscillator divided by 64.

010: SYSCLK derived from Internal Oscillator divided by 32.

011: SYSCLK derived from Internal Oscillator divided by 16.

100: SYSCLK derived from Internal Oscillator divided by 8.

101: SYSCLK derived from Internal Oscillator divided by 4.

110: SYSCLK derived from Internal Oscillator divided by 2.

111: SYSCLK derived from Internal Oscillator divided by 1.

Rev. 1.4

137

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