AS5SS256K36DQ-8.5/IT View Datasheet(PDF) - Micross Components

Part Name

Description

Manufacturer

AS5SS256K36DQ-8.5/IT

256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM

Micross Components 

SSRAM

AS5SS256K36

CLK

ADSP\

ADSC\

ADDRESS

BWE\, GW\,

BWa\ - BWd\

CE\

(Note 2)

ADV\

OE\

Q

READ TIMING3

tKC

tKL

tADSS

tKH

tADSH

tADSS

tAS

A1

tAH

tADSH

A2

t WH

tCES

t WS

t CEH

tAAS

Deselect Cycle

(note 4)

tAAH

tKQLZ

High-Z

tOEQ

t OEHZ

Q(A1)

t KQ

tOELZ

t KQ

tKQX

Q(A2)

Q(A2+1)

(Note 1)

SINGLE READ

ADV\ suspends burst.

tKQHZ

Q(A2+2)

Q(A2+3)

BURST READ

Don’t Care

Q(A2)

Q(A2+1) Q(A2+2)

Burst wraps around to

its initial state

Undefined

NOTE: 1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.

2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is

HIGH, CE2\ is HIGH and CE2 is LOW.

3. Timing is shown assuming that the device was not enabled before entering into this sequence.

4. Outputs are disabled tKQHZ after deselect.

AS5SS256K36

Rev. 4.4 10/13

12

Micross Components reserves the right to change products or specifications without notice.

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