4.9 DVB-ASI Operation
The GS1575B/9075B will also re-clock DVB-ASI at 270 Mb/s. When reclocking DVB-ASI
data set the ASI/177 pin HIGH to prevent a false lock to 177Mb/s. If ASI/177 is not set
HIGH, a false lock may occur since there is a harmonic present in idle patterns (K28.5)
which is very close the 177 Mb/s data rate (EIC 1179). Note that setting the ASI/177 pin
HIGH will disable the 177 Mb/s search when the device is in Auto mode, consequently
the GS1575B/9075B will not lock to that data rate.
4.10 Lock and LOS Indicators
The LOCKED signal is an active high output which indicates when the PLL is locked.
The internal lock logic of the GS1575B/9075B includes a system which monitors the
Frequency Acquisition Loop and the Phase Acquisition Loop as well as a monitor to
detect harmonic lock.
The LOS (Loss of Signal) output is an active HIGH output which indicates the absence of
data transitions at the DDIx input. In order for this output to be asserted, transitions must
not be present for a period of typically 5.14 us. After this output has been asserted, LOS
will deassert typically 5.14 us after the appearance of a transition at the DDIx input. This
timing relationship is shown in Figure 4-4:
5.14 us
5.14 us
DATA
LOS
Figure 4-4: LOS signal timing
NOTE: LOS is sensitive to transitions appearing at the input, and does not distinguish
between transitions caused by input data, and transitions due to noise.
GS1575B / GS9075B HD-LINX® II Multi-Rate SDI
Automatic Reclocker
Data Sheet
40063 - 1
June 2009
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