M28F101-200XK6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M28F101-200XK6 Datasheet PDF : 23 Pages
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M28F101
Table 9B. Read Only Mode AC Characteristics
((TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; 0V ≤ VPP ≤ 6.5V)
M28F101
Symbol Alt
Parameter
-120
-150
-200
Test Condition VCC=5V±10% VCC=5V±10% VCC=5V±10% Unit
EPROM
In terface
EPROM
Interface
EPROM
Interface
Min Max Min Max Min Max
tWHGL
Write Enable High to
Output Enable Low
6
6
6
µs
tAVAV
tRC Read Cycle Time
E = VIL, G = VIL 120
150
200
ns
tAVQV
tACC
Address Valid to
Output Valid
E = VIL, G = VIL
120
150
200 ns
tELQX (1)
tLZ
Chip Enable Low to
Output Transition
G = VIL
0
0
0
ns
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
120
150
200 ns
tGLQX (1)
tOLZ
Output Enable Low to
Output Transition
E = VIL
0
0
0
ns
tGLQV
tOE
Output Enable Low to
Output Valid
E = VIL
50
55
60 ns
tEHQZ (1)
Chip Enable High to
Output Hi-Z
G = VIL
0
55
0
55
0
60 ns
tGHQZ (1)
tDF
Output Enable High to
Output Hi-Z
E = VIL
0
30
0
35
0
40 ns
tAXQX
tOH
Address Transition to
Output Transition
E = VIL, G = VIL
0
0
0
ns
Note: 1. Sampled only, not 100% tested
Erase and Erase Verify Modes. The memory is
erased by first Programming all bytes to 00h, the
Erase command then erases them to FFh. The
Erase Verify command is then used to read the
memory byte-by-byte for a content of FFh. The
Erase Mode is set-up by writing 20h to the com-
mand register. The write cycle is then repeated to
start the erase operation. Erasure starts on the
rising edge of W during this second cycle. Erase is
followed by an Erase Verify which reads an ad-
dressed byte.
Erase Verify Mode is set-up by writing A0h to the
command register and at the same time supplying
the address of the byte to be verified. The rising
edge of W during the set-up of the first Erase Verify
Mode stops the Erase operation. The following
read cycle is made with an internally generated
margin voltage applied; reading FFh indicates that
all bits of the addressed byte are fully erased. The
whole contents of the memory are verified by re-
peating the Erase Verify Operation, first writing the
set-up code A0h with the address of the byte to be
verified and then reading the byte contents in a
second read cycle.
8/23
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