ISL6422 View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

ISL6422

Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

Renesas Electronics 

ISL6422

TABLE 18. CONTROL REGISTER SR8 CONFIGURATION

SR8H SR8M SR8L EN2

X

X VTOP2 VBOT2

FUNCTION

1

1

1

1

X

X

0

0 SR4 is selected

1

1

1

1

X

X

0

0 VSPEN2 = SELVTOP2 = 0, VOUT1 = 13V,

VBOOST1 = 13V + VDROP

1

1

1

1

X

X

0

1 VSPEN2 = SELVTOP2 = 0, VOUT1 = 14V,

VBOOST1 = 14V + VDROP

1

1

1

1

X

X

1

0 VSPEN2 = SELVTOP2 = 0, VOUT1 = 13V,

VBOOST1 = 13V + VDROP

1

1

1

1

X

X

1

1 VSPEN2 = SELVTOP2 = 0, VOUT1 = 14V,

VBOOST1 = 14V + VDROP

1

1

1

1

X

X

0

0 VSPEN2 = 0,SELVTOP2 = 1, VOUT1 = 18V,

VBOOST1 = 18V + VDROP

1

1

1

1

X

X

0

1 VSPEN2 = 0, SELVTOP2 = 1, VOUT1 = 18V,

VBOOST1 = 18V + VDROP

1

1

1

1

X

X

1

0 VSPEN2 = 0, SELVTOP2 = 1, VOUT1 = 19V,

VBOOST1 = 19V + VDROP

1

1

1

1

X

X

1

1 VSPEN2 = 0, SELVTOP2 = 1, VOUT1 = 19V,

VBOOST1 = 19V + VDROP

1

1

1

1

X

X

0

0 VSPEN2 = 1, SELVTOP2 = X, VOUT1 = 13V,

VBOOST1 = 13V + VDROP

1

1

1

1

X

X

0

1 VSPEN2 = 1, SELVTOP2 = X, VOUT1 = 14V,

VBOOST1 = 14V + VDROP

1

1

1

1

X

X

1

0 VSPEN2 = 1, SELVTOP2 = X, VOUT1 = 18V,

VBOOST1 = 18V + VDROP

1

1

1

1

X

X

1

1 VSPEN2 = 1, SELVTOP2 = X, VOUT1 = 19V,

VBOOST1 = 19V + VDROP

1

1

1

0

X

X

X

X PWM and Linear for channel 1 disabled

NOTE: X is a “Don’t Care” for the Write mode.

Received Data (I2C bus READ MODE)

The ISL6422 can provide to the master a copy of the system

register information via the I2C bus in read mode. The read

mode is master-activated by sending the chip address with the

R/W bit set to 1. At the following master-generated clock bits,

the ISL6422 issues a byte on the SDA data bus line (MSB

transmitted first).

At the ninth clock bit, the MCU master can:

• Acknowledge the reception, thus starting the transmission of

another byte from the ISL6422.

• Not acknowledge, thus stopping the read mode

communication.

While the whole register is read back by the microprocessor,

the following read-only bits convey diagnostic information

about the ISL6422.

• OUC1 and OUC2 (Over or Undercurrent bits)

• UV1 and UV2 (Over or Undervoltage bits)

• TPR1 and TPR2 (Tone present bits)

• OTF (Over-temperature fault bit).

Power–On I2C Interface Reset

The I2C interface built into the ISL6422 is automatically reset

at power-on. The I2C interface block will receive a Power OK

logic signal from the UVLO circuit. This signal will go HIGH

when chip power is OK. As long as this signal is LOW, the

interface will not respond to any I2C commands and the

system register SR1 and SR2 are initialized to all zeros, thus

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will be HIGH, the I2C interface becomes operative and the SRs

can be configured by the main microprocessor. About 400mV

of hysteresis is provided in the UVLO threshold to avoid false

triggering of the power-on reset circuit. (I2C comes up with EN

= 0; EN goes HIGH at the same time as (or later than) all other

I2C data for that PWM becomes valid).

FN9190 Rev 2.00

Aug 10, 2007

Page 16 of 20

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