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ISL8200AMMREP View Datasheet(PDF) - Renesas Electronics

Part Name
Description
Manufacturer
ISL8200AMMREP
Renesas
Renesas Electronics 
ISL8200AMMREP Datasheet PDF : 24 Pages
First Prev 21 22 23 24
ISL8200AMM
Thermal Vias
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under
the thermal land. The vias should be from 0.3mm to 0.33mm in
diameter with the barrel plated with 1.0 ounce copper. Although
adding more vias (by decreasing via pitch) will improve the
thermal performance, diminishing returns will be seen as more
and more vias are added. Simply use as many vias as practical
for the thermal land size and your board design rules allow.
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joins. Stencil aperture size to land size ratio should
typically be 1:1. The aperture width may be reduced slightly to
help prevent solder bridging between adjacent I/O lands. To
reduce solder paste volume on the larger thermal lands, it is
recommended that an array of smaller apertures be used
instead of one large aperture. It is recommended that the stencil
printing area cover 50% to 80% of the PCB layout pattern. A
typical solder stencil pattern is shown in the Package Outline
Drawing L23.15x15 on page 24. The gap width between pad to
pad is 0.6mm. The user should consider the symmetry of the
whole stencil pattern when designing its pads. A laser cut,
stainless steel stencil with electropolished trapezoidal walls is
recommended. Electropolishing “smooths” the aperture walls
resulting in reduced surface friction and better paste release,
which reduces voids. Using a trapezoidal section aperture (TSA)
also promotes paste release and forms a "brick like" paste
deposit that assists in firm component placement. A 0.1mm to
0.15mm stencil thickness is recommended for this large pitch
(1.3mm) QFN.
Reflow Parameters
Due to the low mount height of the QFN, "No Clean" Type 3 solder
paste per ANSI/J-STD-005 is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board, so it
is not practical to define a specific soldering profile just for the
QFN. The profile given in Figure 41 is provided as a guideline, to
be customized for varying manufacturing practices and
applications.
300 PEAK TEMPERATURE +215°C~+220°C;
TYPICALLY 60s-70s ABOVE +183°C
250 KEEP LESS THAN 20s WITH 5°C OF PEAK TEMP.
200 SLOW RAMP (3°C/s MAX)
AND SOAK FROM +100°C
TO +150°C FOR 60s~120s
150
100
RAMP RATE 1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 41. TYPICAL REFLOW PROFILE
FN8287 Rev 2.00
June 3, 2015
Page 21 of 24

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