AD5391BSTZ-3(RevF) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5391BSTZ-3
(Rev.:RevF)
(Rev.:RevF)
Analog Devices
AD5391BSTZ-3 Datasheet PDF : 44 Pages
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Data Sheet
AD5390/AD5391/AD5392
TIMING CHARACTERISTICS
SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE
DVDD = 2 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 5. 3-Wire Serial Interface1
Parameter2, 3
Limit at TMIN, TMAX
t1
33
t2
13
t3
13
t4
13
t54
13
t64
33
t7
10
t7
140
t8
5
t9
4.5
t104
36
t11
670
t124
20
t13
20
t14
100/2000
t15
0
t16
100
t17
3
t18
20
t19
40
t205
20
t214
5
t224
8
t234
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns
min/max
ns min
ns min
μs typ
ns min
μs max
ns max
ns min
ns min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC falling edge
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in readback mode
Data setup time
Data hold time
24th SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time, AD5390/AD5391/AD5392; boost mode off
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, Figure 4, and Figure 5.
4 Standalone mode only.
5 Daisy-chain mode only.
t1
SCLK
SYNC
DIN
t7
t3
t4
DB23
t8
t9
24
t2
DB0 DB23
48
t22
t21
DB0
SDO
LDAC
INPUT WORD FOR DAC N
UNDEFINED
INPUT WORD FOR DAC N+1
t20
DB23
DB0
INPUT WORD FOR DAC N
t23
t13
Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)
Rev. F | Page 11 of 44
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