AD9767-EB View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9767-EB

14-Bit, 125 MSPS Dual TxDAC+® D/A Converter

Analog Devices 

AD9767

EVALUATION BOARD

General Description

The AD9767-EB is an evaluation board for the AD9767 14-bit

dual D/A converter. Careful attention to layout and circuit

design, combined with a prototyping area, allow the user to

easily and effectively evaluate the AD9767 in any application

where high resolution, high speed conversion is required.

This board allows the user the flexibility to operate the AD9767

in various configurations. Possible output configurations include

transformer coupled, resistor terminated, and single and differ-

ential outputs. The digital inputs can be used in dual port or

interleaved mode, and are designed to be driven from various

word generators, with the on-board option to add a resistor

network for proper load termination. When operating the

AD9767, best performance is obtained by running the Digital

Supply (DVDD) at +3 V and the Analog Supply (AVDD) at +5 V.

POWER DECOUPLING AND INPUT CLOCKS

RED

B1 TP10 L1

DVDDIN

BEAD

BAN-JACK

B2

DVDD

1 C9

10␮F

2 25V

BLK

TP37

BLK

TP38

BLK

TP39

RED

B3 TP11 L2

AVDDIN

BEAD

BAN-JACK

B4

AVDD

1 C10

10␮F

2 25V

BLK

TP40

BLK

TP41

BLK

TP42

DVDD

1 C7

1 C8

2 0.1␮F 2 0.01␮F

BAN-JACK

TP43

BLK

DGND

BAN-JACK

TP44

BLK

AGND

DCLKIN1

JP9

123

AB

WRT1IN

IQWRT

S1

WHT

TP29

DGND;3,4,5

JP16

CLK1IN

IQCLK

S2

WHT

TP30

DGND;3,4,5

JP5

1 A2B 3

IC

CLK2IN

RESET

S3

WHT

TP31

DGND;3,4,5

JP4

1 A2B 3

IC

WRT2IN

IQSEL

S4

WHT

TP32

DGND;3,4,5

WHT

TP33

JP3

1 A2B 3

1

1

1

1

IC

R1 R2 R3 R4

50⍀ 50⍀ 50⍀ 50⍀

2

2

2

2

SLEEP

1

R13

50⍀

2

DCLKIN2

DVDD

JP2

JP6

123

AB

4

JP1

DVDD

3

PRE

5

J

1

U1 Q

CLK

2

K

6

Q

CLR

TSSOP112

15 DGND;8

DVDD;16

DVDD

AB

123

JP7

/2 CLOCK DIVIDER

WRT1

CLK1

CLK2

WRT2

10

11

PRE

9

J

13

U2 Q

CLK

12

K

7

Q

CLR TSSOP112

14 DGND;8

DVDD;16

SLEEP

RP16

RCOM

1

R1 R2 R3 R4 R5 R6 R7 R8 R9

22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀

2

3

4

5

6

7

8

9

10

INP1 INP2 INP3 INP4 INP5 INP6 INP7 INP8

RP10

RCOM

1

R1 R2 R3 R4 R5 R6 R7 R8 R9

22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀

2

3

4

5

6

7

8

9

10

INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30

RP9

RCOM

1

R1 R2 R3 R4 R5 R6 R7 R8 R9

22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀

2

3

4

5

6

7

8

9

10

INP9 INP10 INP11 INP12 INP13 INP14

INCK1

RP15

RCOM

1

R1 R2 R3 R4 R5 R6 R7 R8 R9

22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀ 22⍀

2

3

4

5

6

7

8

9

10

INP31 INP32 INP33 INP34 INP35 INP36

INCK2

Figure 43. Power Decoupling and Clocks on AD9767 Evaluation Board

–18–

REV. B

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