STA309A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA309A Datasheet PDF : 67 Pages
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Registers
STA309A
7.2
7.2.1
Register description
Configuration register A (0x00)
7
6
5
4
COS1
COS0
DSPB
IR1
1
0
0
0
3
2
1
0
IR0
MCS2
MCS1
MCS0
0
0
1
1
Table 9. MSC bits
Bit RW RST
Name
Description
0
RW
1
MCS0
1
RW
1
MCS1
2
RW
0
MCS2
Master clock select: selects the ratio between the input
I2S sample frequency and the input clock.
The STA309A supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, 192 kHz, and 2.8224 MHz DSD. Therefore, the internal clocks are:
z 65.536 MHz for 32 kHz
z 90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD
z 98.304 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs). The relationship between the input clock and the input sample rate is
determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits
determine the PLL factor generating the internal clock and the IRn bits determine the
oversampling ratio used internally.
Table 10. MSC sample rates
Input sample rate
IR
fs (kHz)
32, 44.1, 48
00
88.2, 96
01
176.4, 192
10
DSD
11
1XX
128 * fs
64 * fs
64 * fs
2 * fs
011
256 * fs
128 * fs
128 * fs
4 * fs
MCS[2:0]
010
384 * fs
192 * fs
192 * fs
6 * fs
001
512 * fs
256 * fs
256 * fs
8 * fs
000
768 * fs
384 * fs
384 * fs
12 * fs
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Doc ID 13855 Rev 4
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