LTC1235CS View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC1235CS

Microprocessor Supervisory Circuit

Linear Technology 

LTC1235

APPLICATI S I FOR ATIO

The 10.7ms allows enough time to execute shut-down

procedure for microprocessor and 831mV of hysteresis

would prevent PFO from going low due to the noise of VIN.

Example 2: The circuit in Figure 9 can be used to measure

the regulated 5V supply to provide early warning of power

failure. Because of variations in the PFI threshold, this

circuit requires adjustment to ensure that the PFI com-

parator trips before the reset threshold is reached. Adjust

R5 such that the PFO output goes low when the VCC supply

reaches the desired level (e.g., 4.85V).

Monitoring the Status of the Battery

C3 can also monitor the status of the memory backup

battery (Figure 10). If desired, the CE OUT can be used to

apply a test load to the battery. Since CE OUT is forced high

in battery backup mode, the test load will not be applied to

the battery while it is in use, even if the microprocessor is

not powered.

watchdog time-out period and reset active time. The

watchdog time-out period is restarted as soon as the reset

outputs are inactive. When either a high-to-low or low-to-

high transition occurs at the WDI pin prior to time-out, the

watchdog time is reset and begins to time out again. To

ensure the watchdog time does not time out, either a high-

to-low or low-to-high transition on the WDI pin must

occur at or less than the minimum time-out period. If the

input to the WDI pin remains either high or low, reset

pulses will be issued every 1.6 seconds typically. The

watchdog timer can be deactivated by floating the WDI pin.

The timer is also disabled when VCC falls below the reset

voltage threshold or VBATT.

The Watchdog Output, WDO, goes low if the watchdog

timer is allowed to time out and remains low until set high

by the next transition on the WDI pin. WDO is also set high

when VCC falls below the reset voltage threshold or VBATT.

+5V

Watchdog Timer

The LTC1235 provides a watchdog timer function to

monitor the activity of the microprocessor. If the micro-

processor does not toggle the Watchdog Input (WDI)

within the time-out period, the reset outputs are forced to

active states for a minimum of 140ms. The watchdog

time-out period is fixed at 1.0 second minimum on the

LTC1235. This time-out period provides adequate time for

many systems to service the watchdog timer immediately

after a reset. Figure 11 shows the timing diagram of

VBATT VCC

R1

PFO

1M

LTC1235

PFI

LOW BATTERY SIGNAL

TO µP I/O PIN

+3V

R2

1M

BACKUP

CE IN

}TO µP I/O PIN

CE OUT GND

RL 20K

OPTIONAL TEST LOAD

LTC1235 F09

Figure 10. Backup Battery Monitor with Optional Test Load

VCC = 5V

WDI

WDO

RESET

t1 = RESET ACTIVE TIME

t2 = WATCHDOG TIME-OUT PERIOD

t2

t2

t1

t1

t1

Figure 11. Watchdog Time-out Period and Reset Active Time

LTC1235 F11

13

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