Pin assignments
Table 1. Pinout list by bus (continued)
Signal
Signal description
Package
pin
number
EC1_RXD0/GPIO3_21
Receive Data
R5
EC1_RXD1/GPIO3_20
Receive Data
N5
EC1_RXD2/GPIO3_19
Receive Data
N6
EC1_RXD3/GPIO3_18
Receive Data
L1
EC1_RX_CLK/GPIO3_23
Receive Clock
M4
EC1_RX_CTL/GPIO3_22
Receive Data Valid
L3
EC1_TXD0/GPIO3_14
Transmit Data
T6
EC1_TXD1/GPIO3_13
Transmit Data
N1
EC1_TXD2/GPIO3_12
Transmit Data
N2
EC1_TXD3/GPIO3_11
Transmit Data
R4
EC1_TX_CTL/GPIO3_15
Transmit Enable
M3
Ethernet Controller (RGMII) 2
EC2_GTX_CLK/GPIO4_28 Transmit Clock Out
T1
EC2_GTX_CLK125/GPIO4_29 Reference Clock
V1
EC2_RXD0/GPIO3_31
Receive Data
R1
EC2_RXD1/GPIO3_30
Receive Data
T2
EC2_RXD2/GPIO3_29
Receive Data
U4
EC2_RXD3/GPIO3_28
Receive Data
R2
EC2_RX_CLK/GPIO4_31
Receive Clock
V6
EC2_RX_CTL/GPIO4_30
Receive Data Valid
U6
EC2_TXD0/GPIO3_27
Transmit Data
W6
EC2_TXD1/GPIO3_26
Transmit Data
U5
EC2_TXD2/GPIO3_25
Transmit Data
U3
EC2_TXD3/GPIO3_24
Transmit Data
V5
EC2_TX_CTL/GPIO4_27
Transmit Enable
R3
DMA
DMA1_DACK0_B/GPIO4_05 DMA1 channel 0 acknowledge
E1
DMA1_DDONE0_B/GPIO4_06 DMA1 channel 0 done
K5
DMA1_DREQ0_B/GPIO4_04 DMA1 channel 0 request
L5
DMA2_DACK0_B/GPIO4_08/ DMA2 channel 0 acknowledge
H1
EVT7_B
DMA2_DDONE0_B/
DMA2 channel 0 done
G3
GPIO4_09/EVT8_B
DMA2_DREQ0_B/GPIO4_07 DMA2 channel 0 request
F3
Power-On-Reset Configuration
cfg_dram_type/IFC_A21
Power-On-Reset Configuration B14
Signal
cfg_gpinput0/IFC_AD00
Power-On-Reset Configuration A13
Signal
Pin
type
Power supply
I
LVDD
I
LVDD
I
LVDD
I
LVDD
I
LVDD
I
LVDD
O LVDD
O LVDD
O LVDD
O LVDD
O LVDD
O LVDD
I
LVDD
I
LVDD
I
LVDD
I
LVDD
I
LVDD
I
LVDD
I
LVDD
O LVDD
O LVDD
O LVDD
O LVDD
O LVDD
O DVDD
O DVDD
I
DVDD
O DVDD
O DVDD
I
DVDD
I
OVDD
I
OVDD
Table continues on the next page...
Notes
1
1
1
1
1
1
1
1
1
1
1, 14
1
1
1
1
1
1
1
1
1
1
1
1
1, 14
1
1
1
1
1
1
1, 4
1, 4
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
24
NXP Semiconductors