T2080NSE8MQB View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
T2080NSE8MQB Datasheet PDF : 186 Pages
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Electrical characteristics
This table shows the power dissipation of the VDD and SnVDD supply for various
operating platform clock frequencies versus the core and DDR clock frequencies when
Altivec power is gated on. See the e6500 core reference manual, section 8.6.4, "Altivec
power up—software-controlled entry" for details on how to enable Altivec.
Table 7. T2080 power dissipation with Altivec power-gated on1
Power
mode
Core freq
(MHz)
Plat
freq
(MHz)
DDR
data
rate
(MT/s
)
FMan
freq
(MHz)
VDD8
(V)
SnVD Junction
D temperature
(ºC)
Core and
platform
power1
(W)
VDD
power
(W)
SnVDD
Notes
Typical 1800
600 2133 700
VID 1.0 65
13.8
12.8 1.0
2, 3, 9
Thermal (low-power
Maximum version)
105
20.2
19.2 1.0
4, 5, 9
22.3
21.3 1.0
5, 6, 7,
9
Typical 1800
600 1867 700
Thermal
(standard
version)
Maximum
VID 1.0 65
105
13.9
12.9 1.0
2, 3
22.4
21.4 1.0
4, 5
24.5
23.5 1.0
5, 6, 7
Typical 1533
600 2133 700
VID 1.0 65
12.8
11.8 1.0
2, 3, 9
Thermal (low-power
Maximum version)
105
16.3
15.3 1.0
4, 5, 9
18.1
17.1 1.0
5, 6, 7,
9
Typical 1533
600 1867 700
Thermal
(standard
version)
Maximum
VID 1.0 65
105
12.7
11.7 1.0
2, 3
18.2
17.2 1.0
4, 5
20.0
19.0 1.0
5, 6, 7
Typical 1200
533 1600 600
VID 1.0 65
11.0
10.0 1.0
2, 3, 9
Thermal (low-power
Maximum version)
105
13.3
12.3 1.0
4, 5, 9
16.1
15.1 1.0
5, 6, 7,
9
Typical 1200
533 1600 600
Thermal
(standard
version)
Maximum
VID 1.0 65
105
11.0
10.0 1.0
2, 3
14.7
13.7 1.0
4, 5
16.1
15.1 1.0
5, 6, 7
Notes:
1. Combined power of VDD and SnVDD with platform at power-on reset default state, the DDR controller and all SerDes banks
active. Does not include I/O power and Altivec is power-gated off.
2. Typical power assumes Dhrystone running with activity factor of 70% (on all cores) and is executing DMA on the platform
with 100% activity factor.
3. Typical power based on nominal, processed device.
4. Thermal power assumes Dhrystone running with activity factor of 70% (on all cores) and executing DMA on the platform at
100% activity factor.
5. Thermal and maximum power are based on worst-case processed device.
6. Maximum power assumes Dhrystone running with work power activity factor at 100% (on all cores) and is executing DMA
on the platform at 115% activity factor.
7. Maximum power provided for power supply design sizing.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
53
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