ST72325S6B5(2007) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72325S6B5
(Rev.:2007)

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

STMicroelectronics 

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

7

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is

set or cleared by software.

0

0: Idle Line

1: Address Mark

R8 T8 SCID M WAKE PCE PS PIE

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received

word when M = 1.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmit-

ted word when M = 1.

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs

are stopped and the end of the current byte trans-

fer in order to reduce power consumption.This bit

is set and cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 4 = M Word length.

This bit determines the word length. It is set or

cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data

transfer (both transmission and reception).

Bit 2 = PCE Parity control enable.

This bit selects the hardware parity control (gener-

ation and detection). When the parity control is en-

abled, the computed parity is inserted at the MSB

position (9th bit if M = 1; 8th bit if M = 0) and parity

is checked on the received data. This bit is set and

cleared by software. Once it is set, PCE is active

after the current byte (in reception and in transmis-

sion).

0: Parity control disabled

1: Parity control enabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the

parity generation/detection is enabled (PCE bit

set). It is set and cleared by software. The parity is

selected after the current byte.

0: Even parity

1: Odd parity

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hard-

ware parity control when a parity error is detected

(PE bit set). It is set and cleared by software.

0: Parity error interrupt disabled

1: Parity error interrupt enabled.

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