ST72325S6B5(2007) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72325S6B5
(Rev.:2007)

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

STMicroelectronics 

I2C BUS INTERFACE (Cont’d)

I2C OWN ADDRESS REGISTER (OAR1)

Read / Write

Reset Value: 0000 0000 (00h)

7

0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

I2C OWN ADDRESS REGISTER (OAR2)

Read / Write

Reset Value: 0100 0000 (40h)

7

0

FR1 FR0 0

0

0 ADD9 ADD8 0

7-bit Addressing Mode

Bit 7:1 = ADD[7:1] Interface address.

These bits define the I2C bus address of the inter-

face. They are not cleared when the interface is

disabled (PE=0).

Bit 0 = ADD0 Address direction bit.

This bit is don’t care, the interface acknowledges

either 0 or 1. It is not cleared when the interface is

disabled (PE=0).

Note: Address 01h is always ignored.

Bit 7:6 = FR[1:0] Frequency bits.

These bits are set by software only when the inter-

face is disabled (PE=0). To configure the interface

to I2C specified delays select the value corre-

sponding to the microcontroller frequency FCPU.

fCPU

< 6 MHz

FR1

FR0

0

0

6 to 8 MHz

0

1

Bit 5:3 = Reserved

10-bit Addressing Mode

Bit 7:0 = ADD[7:0] Interface address.

These are the least significant bits of the I2C bus

address of the interface. They are not cleared

when the interface is disabled (PE=0).

Bit 2:1 = ADD[9:8] Interface address.

These are the most significant bits of the I2C bus

address of the interface (10-bit mode only). They

are not cleared when the interface is disabled

(PE=0).

Bit 0 = Reserved.

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