ST72325S6B5(2007) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72325S6B5
(Rev.:2007)
(Rev.:2007)
STMicroelectronics
ST72325S6B5 Datasheet PDF : 196 Pages
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12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for VDD,
fCPU, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Symbol
Parameter
Conditions
Min
Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
tr(SCK)
tf(SCK)
tsu(SS)
th(SS)
tw(SCKH)
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
ta(SO)
tdis(SO)
tv(SO)
th(SO)
tv(MO)
th(MO)
SPI clock rise and fall time
SS setup time4)
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Master
fCPU=8MHz
Slave
fCPU=8MHz
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
fCPU/128 fCPU/4
0.0625
2
MHz
0
fCPU/2
4
see I/O port pin description
tCPU + 50
120
100
90
100
100
100
100
0
120
240
120
0
120
0
ns
tCPU
Figure 91. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tsu(SS)
ta(SO)
MISO OUTPUT
see note 2
tsu(SI)
tc(SCK)
ttww((SSCCKKLH))
tv(SO)
MSB OUT
th(SI)
BIT6 OUT
th(SS)
th(SO)
tr(SCK)
tf(SCK)
LSB OUT
tdis(SO)
see
note 2
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
4. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1 / fCPU = 125 ns and tsu(SS) = 175 ns.
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