ST72325S6B5(2007) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72325S6B5
(Rev.:2007)

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

STMicroelectronics 

ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

OPT0= FMP_R Flash memory read-out protection

Read-out protection, when selected, provides a

protection against Program Memory content ex-

traction and against write access to Flash memo-

ry.

Erasing the option bytes when the FMP_R option

is selected causes the whole user memory to be

erased first, and the device can be reprogrammed.

Refer to Section 4.3.1 and the ST7 Flash Pro-

gramming Reference Manual for more details.

0: Read-out protection enabled

1: Read-out protection disabled

OPTION BYTE 1

Clock Source

OSCTYPE

1

0

Resonator Oscillator

0

0

Reserved

0

1

Internal RC Oscillator

1

0

External Source

1

1

current source corresponding to the frequency

range of the used resonator. Otherwise, these bits

are used to select the normal operating frequency

range.

OPT7= PKG1 Package selection bit 1

This option bit selects the package.

Version Selected Package Flash size PKG 1

R/AR

LQFP64

32/48/60K 1

C

LQFP48(C)

32/48/60K 1

J

LQFP44/SDIP42

48/60K

0

S/J

LQFP48(S)/LQFP44/

SDIP42

16/32K

1

K

LQFP32/SDIP32

16/32K

0

Note: On the chip, each I/O port has up to 8 pads.

Pads that are not bonded to external pins are

forced in input pull-up configuration after reset.

The configuration of these pads must be kept at

reset state to avoid added current consumption.

In LQFP48(C) devices (PA0, PA1, PB6, PB7,

PD6, PD7, PE3, PE5, PE6, PE7, PF3, PF5) are in

input floating configuration after reset. Refer to

Note 4 on page 16.

OPT6 = RSTC RESET clock cycle selection

This option bit selects the number of CPU cycles

applied during the RESET phase and when exiting

HALT mode. For resonator oscillators, it is advised

to select 4096 due to the long crystal stabilization

time.

0: Reset phase with 4096 CPU cycles

1: Reset phase with 256 CPU cycles

Typ. Freq. Range

1~2MHz

2~4MHz

4~8MHz

8~16MHz

OSCRANGE

2

1

0

0

0

0

0

0

1

0

1

0

0

1

1

OPT0 = PLLOFF PLL activation

This option bit activates the PLL which allows mul-

tiplication by two of the main input clock frequency.

The PLL is guaranteed only with an input frequen-

cy between 2 and 4MHz, for this reason the PLL

must not be used with the internal RC oscillator.

0: PLL x2 enabled

1: PLL x2 disabled

CAUTION: the PLL can be enabled only if the

“OSC RANGE” (OPT3:1) bits are configured to “

2~4MHz”. Otherwise, the device functionality is

not guaranteed.

OPT5:4 = OSCTYPE[1:0] Oscillator Type

These option bits select the ST7 main clock

source type.

OPT3:1 = OSCRANGE[2:0] Oscillator range

When the resonator oscillator type is selected,

these option bits select the resonator oscillator

181/196

Share Link: