ST72325S6B5(2007) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72325S6B5
(Rev.:2007)

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

STMicroelectronics 

INTERRUPTS (Cont’d)

Table 9. Interrupt Mapping

N°

Source

Block

Description

RESET Reset

TRAP

Software interrupt

0

TLI

External top level interrupt

1

MCC/RTC/ Main clock controller time base interrupt

CSS

Safe oscillator activation interrupt

2

ei0

External interrupt port A3..0

Register

Label

N/A

EICR

MCCSR-

SICSR

Exit

Priority

Order

from

HALT/

ACTIVE

HALT

Address

Vector

yes FFFEh-FFFFh

no FFFCh-FFFDh

yes FFFAh-FFFBh

Higher yes

Priority

yes

FFF8h-FFF9h

FFF6h-FFF7h

3

ei1

External interrupt port F2..0

yes FFF4h-FFF5h

N/A

4

ei2

External interrupt port B3..0

5

ei3

External interrupt port B7..4

6

Not used

7

SPI

SPI peripheral interrupts

8

TIMER A TIMER A peripheral interrupts

9

TIMER B TIMER B peripheral interrupts

10

SCI

SCI Peripheral interrupts

11

AVD

Auxiliary Voltage detector interrupt

12

I2C

I2C Peripheral interrupts

13

PWM ART PWM ART interrupt

SPICSR

TASR

TBSR

SCISR

Lower

Priority

SICSR

(see periph)

ARTCSR

yes

yes

yes1

no

no

no

no

no

yes2

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

FFE2h-FFE3h

FFE0h-FFE1h

Notes:

1. Exit from HALT possible when SPI is in slave mode.

2. Exit from HALT possible when PWM ART is in external clock mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

The external interrupt sensitivity is controlled by

the IPA, IPB and ISxx bits of the EICR register

(Figure 25). This control allows to have up to 4 fully

independent external interrupt source sensitivities.

Each external interrupt source can be generated

on four (or five) different events on the pin:

■ Falling edge

■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

■ Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity

bits in the EICR register can be modified only

when the I1 and I0 bits of the CC register are both

set to 1 (level 3). This means that interrupts must

be disabled before changing sensitivity.

The pending interrupts are cleared by writing a dif-

ferent value in the ISx[1:0], IPA or IPB bits of the

EICR.

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