ST72325
Pin n°
Pin Name
Level
Port
Input
Output
Main
function
(after
reset)
Alternate function
28 31 PB0/PWM3
I/O CT
X ei2
PWM Output 3
X X Port B0 Caution: Negative current injec-
tion not allowed on this pin5)
29 32 PB3/PWM0
I/O CT
X
ei2
X X Port B3 PWM Output 0
30 1 PB4 (HS)/ARTCLK I/O CT HS X ei3
X X Port B4 PWM-ART External Clock
31 2 PD0/AIN0
I/O CT
XX
X X X Port D0 ADC Analog Input 0
32 3 PD1/AIN1
I/O CT
XX
X X X Port D1 ADC Analog Input 1
Notes for Table 1 and Table 2:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See See “I/O PORTS” on page 50. and Section 12.8 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-
lator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for
more details.
4. On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are in input
pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid add-
ed current consumption.
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