ST72325J7B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72325J7B5

8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE

STMicroelectronics 

ST72325

15 KNOWN LIMITATIONS

15.1 ALL DEVICES

15.1.1 Unexpected Reset Fetch

If an interrupt request occurs while a “POP CC” in-

struction is executed, the interrupt controller does

not recognise the source of the interrupt and, by

default, passes the RESET vector address to the

CPU.

Workaround

To solve this issue, a “POP CC” instruction must

always be preceded by a “SIM” instruction.

15.1.2 Clearing active interrupts outside

interrupt routine

When an active interrupt request occurs at the

same time as the related flag is being cleared, an

unwanted reset may occur.

Note: clearing the related interrupt mask will not

generate an unwanted reset

Concurrent interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

Perform SIM and RIM operation before and after

resetting an active interrupt request.

Example:

SIM

reset interrupt flag

RIM

Nested interrupt context:

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine with higher or identical priority level

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

PUSH CC

SIM

reset interrupt flag

POP CC

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