ST72325J7B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72325J7B5

8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE

STMicroelectronics 

ST72325

16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Read/Write (bits 7:3 read only)

Reset Value: xxxx x0xx (xxh)

7

0

ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

register, then read or write the low byte of the

IC1R (IC1LR) register.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC1R (OC1LR) reg-

ister.

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

Note: Reading or writing the ACLR register does

not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC2R (OC2LR) reg-

ister.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it

freezes the timer prescaler and counter and disa-

bled the output functions (OCMP1 and OCMP2

pins) to reduce power consumption. Access to the

timer registers is still available, allowing the timer

configuration to be changed, or the counter reset,

while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

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