CY8C5266LTI-LP029 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY8C5266LTI-LP029

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 5LP: CY8C52LP Family

Datasheet

Bus Clock

EM_Clock

EM_Addr

Figure 11-59. Synchronous Write and Read Cycle Timing, No Wait States

Tbus_clock

EM_CE

EM_ADSC

EM_WE

EM_OE

EM_Data

Twr_setup

Write Cycle

Minimum of 4 bus clock cycles between successive EMIF accesses

Trd_setup

Trd_hold

Read Cycle

Table 11-51. Synchronous Write and Read Timing Specifications[66]

Parameter

Description

Fbus_clock Bus clock frequency[67]

Tbus_clock Bus clock period[68]

Twr_Setup Time from EM_data valid to rising edge of

EM_Clock

Trd_setup Time that EM_data must be valid before rising

edge of EM_OE

Trd_hold

Time that EM_data must be valid after rising

edge of EM_OE

Conditions

Min

Typ

–

–

30.3

–

Tbus_clock – 10

–

5

–

5

–

Max

Units

33

MHz

–

ns

–

ns

–

ns

–

ns

Notes

66. Based on device characterization (Not production tested).

67. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 68.

68. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.

Document Number: 001-84933 Rev. *L

Page 96 of 114

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