M24M01-R M24M01-DF
DC and AC parameters
Table 15. 1 MHz AC characteristics
Symbol Alt.
Parameter
Min.
Max.
Unit
fC
fSCL Clock frequency
0
tCHCL
tHIGH Clock pulse width high
300
tCLCH
tLOW Clock pulse width low
400
tXH1XH2
tR Input signal rise time
(1)
tXL1XL2
tF Input signal fall time
(1)
tQL1QL2(8)
tF SDA (out) fall time
-
tDXCX
tSU:DAT Data in setup time
80
tCLDX
tHD:DAT Data in hold time
0
tCLQX(2)
tDH Data out hold time
50
tCLQV(3)
tAA Clock low to next data valid (access time)
-
tCHDL
tSU:STA Start condition setup time
250
tDLCL
tHD:STA Start condition hold time
250
tCHDH tSU:STO Stop condition setup time
250
tDHDL
tBUF
Time between Stop condition and next Start
condition
500
tWLDL(4)(8) tSU:WC WC set up time (before the Start condition)
0
tDHWH(5)(8) tHD:WC WC hold time (after the Stop condition)
1
tW
tWR Write time
-
tNS(6)
-
Pulse width ignored (input filter on SCL and
SDA)
-
1
-
-
(1)
(1)
120
-
-
-
500
-
-
-
-
-
-
5
50(7)
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ns
1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
fC < 1 MHz.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
3.
t0C.7LQVVCiCs,thaesstuimmein(gfrothmatththeefaRllbinugs
edge of
× Cbus
SCL) required by the SDA
time constant is within the
vbauluselisnesptoecriefiaecdhineiFthigeur r0e.313V.CC
or
4. WC=0 set up time condition to enable the execution of a WRITE command.
5. WC=0 hold time condition to enable the execution of a WRITE command.
6. Characterized only, not tested in production.
7.
The previous products were specified
tNS(max)=50ns is the value defined by
wthiethIa²Ct-NbSu(smsapxe) cloifnicgaetirotnh.an
50
ns,
it
should
be
noted
that
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