Electrical characteristics
STM32WB55xx STM32WB35xx
Table 75. NRST pin characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST inputï€
low level voltage
VIH(NRST)
NRST inputï€
high level voltage
-
-
-
0.3 x VDD
V
-
0.7 x VDD
-
-
Vhys(NRST)
NRST Schmitt trigger
voltage hysteresis
-
-
200
-
mV
RPU
Weak pull-up
equivalent resistor(2)
VIN = VSS
25
40
55
kΩ
VF(NRST)
NRST inputï€
filtered pulse
-
-
-
VNF(NRST)
NRST inputï€
not filtered pulse
1.71 V ≤ VDD ≤ 3.6 V
350
-
70
ns
-
1. Guaranteed by design.
2.
The pull-up is designed
the series resistance is
mwiitnhimaatrlu(e~1re0s%is)t.ance
in
series
with
a
switchable
PMOS.
This
PMOS
contribution
to
Figure 28. Recommended NRST pin protection
External
reset circuit(1)
NRST(2)
0.1 μF
VDD
RPU
Filter
Internal reset
MS19878V3
1. The reset network protects the device against parasitic resets.
2. TTahbeleus7e5r,motuhsetrewnisseurtehethraetstehtewleillvneol ot nbethteakNeRn SinTtopaincccoaunngtobybethloewdtehveicVeI.L(NRST) max level specified in
3. The external capacitor on NRST must be placed as close as possible to the device.
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DS11929 Rev 10