STM32WB55xx STM32WB35xx
Electrical characteristics
Table 77. ADC characteristics(1) (2) (3) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tLATR
Trigger conversion
latency Regular and
CKMODE = 00
CKMODE = 01
injected channels
CKMODE = 10
without conversion abort
CKMODE = 11
tLATRINJ
Trigger conversion
latency Injected
channels aborting a
regular conversion
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
ts
Sampling time
fADC = 64 MHz
-
tADCVREG_STUP
ADC voltage regulator
start-up time
-
tCONV
Total conversion timeï€
fADC = 64 MHzï€
Resolution = 12 bits
(including sampling time)
Resolution = 12 bits
IDDA(ADC)
IDDV_S(ADC)
IDDV_D(ADC)
ADC consumption from
the VDDA supply
ADC consumption from
the VREF+ single ended
mode
ADC consumption from
the VREF+ differential
mode
fs = 4.26 Msps
fs = 1 Msps
fs = 10 ksps
fs = 4.26 Msps
fs = 1 Msps
fs = 10 ksps
fs = 4.26 Msps
fs = 1 Msps
fs = 10 ksps
1.5
2
2.5
-
-
2.0
-
-
2.25
-
-
2.125
2.5
3
3.5
-
-
3.0
-
-
3.25
-
-
3.125
0.039
-
10.0
2.5
-
640.5
-
-
20
0.234
-
1.019
ts + 12.5 cycles for successive
approximations = 15 to 653
-
730
830
-
160
220
-
16
50
-
130
160
-
30
40
-
0.6
2
-
250
310
-
60
70
-
1.3
3
1/fADC
1/fADC
µs
1/fADC
µs
µs
1/fADC
µA
µA
µA
1. Guaranteed by design
2.
The I/O
VDDA <
analog switch voltage booster
2.4V). It is disable when VDDA
is enabled
≥ 2.4 V.
when
VDDA
<
2.4
V
(BOOSTEN
=
1
in
the
SYSCFG_CFGR1
when
3. SMPS in bypass mode.
4. RVeRfEeFr +tocSanecbteionint4e:rPnainlloyuctsonannedcpteind dtoesVcDrDipAtioanndfoVr RfuErFth- ecar ndebteaiilns.ternally connected to VSSA, depending on the package.ï€
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