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STM32WB55VCQ6TR View Datasheet(PDF) - STMicroelectronics

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STM32WB55VCQ6TR Datasheet PDF : 193 Pages
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Electrical characteristics
STM32WB55xx STM32WB35xx
Table 96. SAI characteristics(1)
Symbol
Parameter
Conditions
Min Max Unit
fMCLK
SAI main clock output
-
Master transmitter
2.7 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
50
- 23.5
Master transmitter
1.65 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
16
Master receiver
Voltage Range 1
fCK
SAI clock frequency(2) Slave transmitter
2.7 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
16
MHz
-
26
Slave transmitter
1.65 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
20
Slave receiver
Voltage Range 1
-
32
Voltage Range 2
-
8
tv(FS)
FS valid time
Master mode
2.7 V ≤ VDD ≤ 3.6 V
Master mode
1.65 V ≤ VDD ≤ 3.6 V
-
21
-
30
th(FS)
FS hold time
Master mode
10
-
tsu(FS)
FS setup time
Slave mode
1.5
-
th(FS)
FS hold time
Slave mode
2.5
-
tsu(SD_A_MR) Data input setup time Master receiver
tsu(SD_B_SR)
Slave receiver
1
-
1.5
-
th(SD_A_MR) Data input hold time
th(SD_B_SR)
Master receiver
Slave receiver
6.5
-
2.5
-
ns
tv(SD_B_ST)
Data output valid time
Slave transmitter (after enable edge)
2.7 V ≤ VDD ≤ 3.6 V
Slave transmitter (after enable edge)
1.65 V ≤ VDD ≤ 3.6 V
-
-
19
25
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge)
10
-
tv(SD_A_MT)
Data output valid time
Master transmitter (after enable edge)
2.7 V ≤ VDD ≤ 3.6 V
Master transmitter (after enable edge)
1.65 V ≤ VDD ≤ 3.6 V
-
-
18.5
25
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10
-
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
166/193
DS11929 Rev 10

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