STM32WB35VEY6TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32WB35VEY6TR

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5 and 802.15.4 radio solution

STMicroelectronics 

Functional overview

STM32WB55xx STM32WB35xx

Table 3. Access status vs. readout protection level and execution modes

Area

Protection

level

User execution

Read

Write

Erase

Debug, boot from SRAM or boot

from system memory (loader)

Read

Write

Erase

Main

1

memory

2

System

1

memory

2

Option

1

bytes

2

Backup

1

registers

2

SRAM2a

1

SRAM2b

2

Yes

Yes

Yes

No

Yes

Yes

Yes

N/A

Yes

No

No

Yes

Yes

No

No

N/A

Yes

Yes

Yes

Yes

Yes

No(1)

No(1)

N/A

Yes

Yes

N/A(2)

No

Yes

Yes

N/A

N/A

Yes

Yes

Yes(2)

No

Yes

Yes

Yes

N/A

No

No

N/A

N/A

No

No

N/A

N/A

Yes

Yes

N/A

N/A

No

N/A(2)

N/A

N/A

No

No(2)

N/A

N/A

1. The option byte can be modified by the RF subsystem.

2. Erased when RDP changes from Level 1 to Level 0.

 Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 4-Kbyte granularity.

 Proprietary code readout protection (PCROP): two parts of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only:

it can only be reached by the STM32 CPU, as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

Two areas can be selected, with 2-Kbyte granularity. An additional option bit

(PCROP_RDP) makes possible to select if the PCROP area is erased or not when the

RDP protection is changed from Level 1 to Level 0.

A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be

accessed by the host CPU1.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

 single error detection and correction

 double error detection

 the address of the ECC fail can be read in the ECC register

The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis.

A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.

20/193

DS11929 Rev 10

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