STM32WB55VC View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32WB55VC
STMicroelectronics
STM32WB55VC Datasheet PDF : 193 Pages
| |||
STM32WB55xx STM32WB35xx
Functional overview
3.7.6
Reset mode
To improve the consumption under reset, the I/Os state under and after reset is “analog
state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.8
Note:
VBAT operation
The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers)
from an external battery, an external supercapacitor, or from VDD when no external battery
nor an external supercapacitor are present. Three anti-tamper detection pins are available
in VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
When the microcontroller is supplied only from VBAT, external interrupts and RTC
alarm/events do not exit it from VBAT operation.
3.9
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU1 resources and, consequently, reducing
power supply consumption. In addition, these hardware connections result in fast and
predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run and Sleep, Stop 0, Stop 1 and Stop 2 modes.
Table 9. STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix
Source
Destination
Action
TIMx
COMPx
ADC1
TIMx
ADC1
DMA
COMPx
Timers synchronization or chaining
Conversion triggers
Memory to memory transfer trigger
Comparator output blanking
TIM1
TIM2
Timer input channel, trigger, break
from analog signals comparison
LPTIMERx
Low-power timer triggered by analog
signals comparison
TIM1
Timer triggered by analog watchdog
YYYY - -
YYYY - -
YYYY - -
YYYY - -
YYYY - -
Y Y Y Y Y Y(1)
YYYY - -
DS11929 Rev 10
39/193
57
Share Link: 