STM32WB55CCY7ATR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32WB55CCY7ATR

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5 and 802.15.4 radio solution

STMicroelectronics 

STM32WB55xx STM32WB35xx

Functional overview

3.13.2

The NVIC benefits are the following:

 Closely coupled NVIC gives low latency interrupt processing

 Interrupt entry vector table address passed directly to the core

 Allows early processing of interrupts

 Processing of late arriving higher priority interrupts

 Support for tail chaining

 Processor state automatically saved

 Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

Extended interrupts and events controller (EXTI)

The EXTI manages wakeup through configurable and direct event inputs. It provides 

wake-up requests to the Power control, and generates interrupt requests to the CPUx NVIC

and events to the CPUx event input.

Configurable events/interrupts come from peripherals able to generate a pulse, and make it

possible to select the Event/Interrupt trigger edge and/or a SW trigger.

Direct events/interrupts are coming from peripherals having their own clearing mechanism.

3.14

Analog to digital converter (ADC)

The device embeds a successive approximation analog-to-digital converter with the

following features:

 12-bit native resolution, with built-in calibration

 Up to 16-bit resolution with 256 oversampling ratio

 4.26 Msps maximum conversion rate with full resolution

– Down to 39 ns sampling time

– Increased conversion rate for lower resolution (up to 7.11 Msps for 6-bit

resolution)

 Up to sixteen external channels and three internal channels: internal reference

voltages, temperature sensor

 Single-ended and differential mode inputs

 Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases

linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

 Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: two groups

of analog signals conversions can be programmed to differentiate background and

high-priority real-time conversions

– The ADC supports multiple trigger inputs for synchronization with on-chip timers

and external signals

– Results stored into three data register or in SRAM with DMA controller support

DS11929 Rev 10

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