STM32WB55xx STM32WB35xx
Functional overview
3.20.3
3.20.4
– Features four independent channels for input capture/output compare, PWM or
one-pulse mode output. Can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
– The counter can be frozen in debug mode.
– Independent DMA request generation, support of quadrature encoders.
ï‚· TIM16 and TIM17
– General-purpose timers with mid-range features:
– 16-bit auto-reload upcounters and 16-bit prescalers.
– 1 channel and 1 complementary channel.
– All channels can be used for input capture/output compare, PWM or one-pulse
mode output.
– The timers can work together via the Timer Link feature for synchronization or
event chaining. The timers have independent DMA request generation.
– The counters can be frozen in debug mode.
Low-power timer (LPTIM1 and LPTIM2)
The devices embed two low-power timers, having an independent clock running in Stop
mode if they are clocked by LSE, LSIx or by an external clock. They are able to wakeup the
system from Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 modes.
The low-power timers support the following features:
ï‚· 16-bit up counter with 16-bit autoreload register
ï‚· 16-bit compare register
ï‚· Configurable output: pulse, PWM
ï‚· Continuous/ one shot mode
ï‚· Selectable software/hardware input trigger
ï‚· Selectable clock source
– Internal clock sources: LSE, either LSI1 or LSI2, HSI16 or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application)
ï‚· Programmable digital glitch filter
ï‚· Encoder mode (LPTIM1 only)
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
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