STM32WB55RGQ7ATR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32WB55RGQ7ATR

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5 and 802.15.4 radio solution

STMicroelectronics 

Functional overview

STM32WB55xx STM32WB35xx

 Interruption sources when enabled:

– Errors

– FIFO requests

 DMA interface with two dedicated channels to handle access to the dedicated

integrated FIFO of the SAI audio sub-block.

The PDM (Pulse Density Modulation) block allows the user to manage up to three digital

microphone pairs (with two different clocks). This block performs Right and Left microphone 

de-interleaving and time alignment through programmable delay lines in order to properly

feed the SAI.

3.27

Quad-SPI memory interface (QUADSPI)

The Quad-SPI is a specialized communication interface targeting single, dual or quad SPI

Flash memories. It can operate in any of the three following modes:

 Indirect mode: all the operations are performed using the QUADSPI registers

 Status polling mode: the external memory status register is periodically read and an

interrupt can be generated in case of flag setting

 Memory-mapped mode: the external Flash memory is mapped and is seen by the

system as if it were an internal memory. This mode can be used for the Execute In

Place (XIP)

The Quad-SPI interface supports:

 Three functional modes: indirect, status-polling, and memory-mapped

 SDR and DDR support

 Fully programmable opcode for both indirect and memory mapped mode

 Fully programmable frame format for both indirect and memory mapped mode

 Each of the five following phases can be configured independently (enable, length,

single/dual/quad communication)

– Instruction phase

– Address phase

– Alternate bytes phase

– Dummy cycles phase

– Data phase

 Integrated FIFO for reception and transmission

 8, 16, and 32-bit data accesses are allowed

 DMA channel for indirect mode operations

 Programmable masking for external Flash memory flag management

 Timeout management

 Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

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DS11929 Rev 10

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