STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics

STLC5464 Datasheet PDF : 83 Pages

First Prev 81 82 83

STLC5464

IX - EXTERNAL REGISTERS (continued)

ODD : Odd byte number

ODD = 1, one byte has been written in the following word.

ODD = 0, two bytes have been written in the following word.

In case of V* protocol ODD,A,F,L bits are respectively 1,0,1,1.

M1/8 : New Byte received twice consecutively if GCI Protocol has been validated.

Byte received once if V* Protocol has been validated.

M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated.

This byte is at ”1” in case of V* protocol.

IX.6.2 - Receive Monitor Interrupt when TSV = 1

TSV : Time Stamping Validated (bit of GCR Register)

bit15

bit8 bit7

bit 0

G0 A2 A1 A0

ODD A

M18 M17 M16 M15 M14 M13 M12 M11 M8 M7 M6 M5 M4 M3 M2 M1

T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

These four words are located in the Monitor interrupt queue ; IQSR Register indicates the size of this

interrupt queue located in the external memory.

NS : New Status.

Before writing the features of event in the external memory the Interrupt Controller reads the

NS bit :

if NS = 0, the Interrupt Controller stores two new bytes M1/8 and M11/18 then puts NS bit at ‘1’

when it writes the status of these two bytes which has been received.

if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).

G0 : G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.

G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.

: Last byte

L = 1, the following word contains the Last byte of message.

L = 0, the Last byte of message is not the following word.

: First byte

F=1, the following word contains the First byte of message.

F=0, the First byte of message is not the following word.

: Abort

A=1, Received message has been aborted.