CS493102-CL View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS493102-CL

Multi-Standard Audio Decoder Family

Cirrus Logic 

CS49300 Family DSP

waiting for a hard reset. The host should re-try

steps 1 through 3 and if failure is met again, the

serial communication timing and protocol

should be inspected.

5) After receiving the BOOT_START byte, the

host should write the downloadable image

(from the .LD file).

6) The end of the .LD file contains a three byte

checksum. If the checksum is good after

download, the CS493XX will send a

BOOT_SUCCESS message (0x02) to the

host. If the checksum was bad, the CS493XX

responds with the BAD_CHECKSUM message

byte (0xFF) and spins, waiting for hard reset.

7) After reading out the BOOT_SUCCESS byte,

the

host

should

send

the

BOOT_SUCCESS_RECEIVED message

(0x000005) which will cause an internal

application code reset and allow the

downloaded application to run.

8) After waiting 5ms to allow the downloaded

application to initialize, the host can send

configuration messages for both hardware and

software configuration.

8.1.2. Parallel Download Sequence

The following is a detailed description of a parallel

download sequence for the CS493XX.

Note: When reading from the chip in a parallel

communication mode, the host must read the

HOSTCTL register and test the HOUTRDY bit

before starting the read cycle.

1) A download sequence is started when the host

issues a hard reset and holds the mode pins

appropriately (WR, RD, and PSEL).

2) The host should then send the boot message

DOWNLOAD_BOOT (0x000004). This causes

the CS493XX to initialize itself for download.

3) If the initialization was successful the

CS493XX sends out the boot message

BOOT_START (0x01) and the host should

proceed to step 5.

4) If initialization fails, the CS493XX sends out an

INIT_FAILURE boot message byte (0xFD or

0xFE), INVALID_MSG byte (0xFB), or

BOOT_ERROR byte (0xFA or 0xFC) and spins

waiting for a hard reset. The host should re-try

steps 1 through 3 and if failure is met again, the

serial communication timing and protocol

should be inspected.

5) After receiving the BOOT_START byte, the

host should write the downloadable image

(from the .LD file).

6) The end of the .LD file contains a three byte

checksum. If the checksum is good after

download, the CS493XX will send a

BOOT_SUCCESS message (0x02) to the

host. If the checksum was bad, the CS493XX

responds with the BAD_CHECKSUM message

byte (0xFF) and spins, waiting for hard reset.

7) After reading out the BOOT_SUCCESS byte,

the

host

should

send

the

BOOT_SUCCESS_RECEIVED message

(0x000005) which will cause an internal

application code reset and allow the

downloaded application to run.

8) After waiting 5ms to allow the downloaded

application to initialize, the host can send

configuration messages for both hardware and

software configuration.

8.2. Autoboot

Autoboot is a feature available on all DSPs in the

CS493XX family which gives the decoder the

ability to load application code into itself from an

external memory. Because external memory is

accessed through the external memory interface,

autoboot restricts the host control modes to serial

communication (I2C or SPI). For this section the

external memory interface shown in Figure 30,

"External Memory Interface" on page 53 can be

referenced.

RESET and ABOOT are the control pins which are

used to initiate an autoboot operation by the host

controller. It is important to be aware that the

ABOOT pin also serves as the INTREQ pin, which

means that it will be driven by the CS493XX when

not in reset. Due to this constraint, ABOOT should

be connected to an open-drain output of the

microcontroller so as to allow the specified pull-up

resistor to generate a logic high level. At the

completion of a successful download, INTREQ

(ABOOT) becomes an output and the host should

no longer drive it.

DS339F7

57

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