AD9742-EB View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9742-EB Datasheet PDF : 32 Pages
| |||
Data Sheet
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship
between the position of the clock edges and the time at which
the input data changes. The AD9742 is rising edge triggered,
and so exhibits dynamic performance sensitivity when the data
transition is close to this edge. In general, the goal when applying
the AD9742 is to make the data transition close to the falling
clock edge. This becomes more important as the sample rate
increases. Figure 27 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement,
while at higher rates, more care must be taken.
75
70
65
60
20MHz SFDR
55
50MHz SFDR
50
45
40
50MHz SFDR
35
–3
–2
–1
0
1
2
3
ns
Figure 27. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz
Sleep Mode Operation
The AD9742 has a power-down function that turns off the
output current and reduces the supply current to less than 6 mA
over the specified supply range of 2.7 V to 3.6 V and temperature
range. This mode can be activated by applying a Logic Level 1
to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω
AVDD. This digital input also contains an active pull-down circuit
that ensures that the AD9742 remains enabled if this input is
left disconnected. The AD9742 takes less than 50 ns to power
down and approximately 5 µs to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9742 is dependent on several
factors that include:
• The power supply voltages (AVDD, CLKVDD, and DVDD)
• The full-scale current output IOUTFS
• The update rate fCLOCK
• The reconstructed digital input waveform
AD9742
The power dissipation is directly proportional to the analog supply
current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly
proportional to IOUTFS, as shown in Figure 28, and is insensitive to
fCLOCK. Conversely, IDVDD is dependent on both the digital input
waveform, fCLOCK, and digital supply DVDD. Figure 29 shows
IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
35
30
25
20
15
10
0
2
20
18
16
14
12
10
8
6
4
2
0
0.01
12
4
6
8 10 12 14 16 18 20
IOUTFS (mA)
Figure 28. IAVDD vs. IOUTFS
210MSPS
165MSPS
125MSPS
65MSPS
0.1
1
RATIO (fOUT/fCLOCK)
Figure 29. IDVDD vs. Ratio @ DVDD = 3.3 V
10
8
PECL
6
DIFF
4
SE
2
0
0
50
100
150
200
250
fCLOCK (MSPS)
Figure 30. ICLKVDD vs. fCLOCK and Clock Mode
Rev. C | Page 15 of 32
Share Link: 