AD14060(RevB) View Datasheet(PDF) - Analog Devices
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AD14060 Datasheet PDF : 48 Pages
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AD14060/AD14060L
SYNCHRONOUS READ/WRITE—BUS MASTER
Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave
ADSP 2106x in multiprocessor memory space. These synchronous switching characteristics are also valid during asynchronous memory
reads and writes (see the Memory Read—Bus Master and Memory Write—Bus Master sections).
When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see the Synchronous Read/Write—Bus Slave section). The slave ADSP-2106x must also meet these bus master timing
requirements for data and acknowledge setup and hold times.
Table 10. Specifications
Parameter
Timing Requirements:
tSSDATI
Data Setup before CLKIN
tHSDATI
tDAAK
Data Hold after CLKIN
ACK Delay after Address, MSx, SW, BMS1, 2
tSACKC
ACK Setup before CLKIN2
tHACKC
ACK Hold after CLKIN
Switching Characteristics:
tDADRO Address, MSx, BMS, SW, Delay after CLKIN1
tHADRO Address, MSx, BMS, SW, Hold after CLKIN
tDPGC
PAGE Delay after CLKIN
tDRDO
RD High Delay after CLKIN
tDWRO
WR High Delay after CLKIN
tDRWL
RD/WR Low Delay after CLKIN
tSDDATO
tDATTR
Data Delay after CLKIN
Data Disable after CLKIN3
tDADCCK ADRCLK Delay after CLKIN
tADRCK
ADRCLK Period
tADRCKH ADRCLK Width High
tADRCKL ADRCLK Width Low
5V
Min
Max
3 + DT/8
4 − DT/8
6.5 + DT/4
−0.5 − DT/4
13.5 + 7 DT/8 + W
−1 − DT/8
9 + DT/8
−2 − DT/8
−3 − 3 DT/16
8 + DT/4
0 − DT/8
4 + DT/8
tCK
(tCK/2 − 2)
(tCK/2 − 2)
8 − DT/8
17 + DT/8
+5 − DT/8
+5 − 3 DT/16
13.5 + DT/4
20 + 5 DT/16
8 − DT/8
11 + DT/8
3.3 V
Min
Max
3 + DT/8
4 − DT/8
6.5 + DT/4
−0.5 − DT/4
13.5 + 7 DT/8 + W
−1 − DT/8
9 + DT/8
−2 − DT/8
−3 − 3 DT/16
8 + DT/4
0 − DT/8
4 + DT/8
tCK
(tCK/2 − 2)
(tCK/2 − 2)
8 − DT/8
17 + DT/8
+5 − DT/8
+5 − 3 DT/16
13.5 + DT/4
20.25 + 5 DT/16
8 – DT/8
11 + DT/8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = number of wait states specified in WAIT register × tCK.
1 For MSx, SW, BMS, the falling edge is referenced.
2 ACK delay/setup: User must meet tDAAK, tDSAK, or synchronous specification, tSACKC.
3 See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
Rev. B | Page 10 of 48
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