ADP5051 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADP5051

Integrated Power Solution with Quad Buck Regulators, Supervisory Circuit, and I2C Interface

Analog Devices 

ADP5051

FUNCTIONAL BLOCK DIAGRAM

EN1

COMP1

FB1

EN2

COMP2

FB2

RT

SYNC/MODE

SS12

SS34

PWRGD

CHANNEL 1—BUCK

0.8V –

+

1MΩ

CLK1

+

OCP –

HICCUP

AND

LATCH-UP

SLOPE

COMP

+

CMP1

–

0.8V

VID1

0.72V

+

EA1

–

CLK1

FREQ

FOLDBACK

OVP

– LATCH-UP

0.88V +

+

– PWRGD1

CHANNEL 2—BUCK

UVLO1

ACS1

VREG

Q1

DRIVER

CONTROL

LOGIC

AND MOSFET

DRIVER WITH

ANTICROSS

PROTECTION

VREG

DRIVER

ZERO

CROSS

CURRENT-LIMIT

SELECTION

CURRENT BALANCE

DUPLICATE

CHANNEL 1

OSCILLATOR

SOFT START

DECODER

HOUSE KEEPING

LOGIC

PVIN1

VREG

INTERNAL

REGULATOR

POWER-ON

RESET

I2C AND

REGISTERS

PVIN1

BST1

SW1

DL1

PGND

PVIN2

BST2

DL2

SW2

VREG

VDD

VDDIO

SCL

SDA

INT

EN3

COMP3

FB3

EN4

COMP4

FB4

WDI

MR

CHANNEL 3—BUCK

0.8V –

+

1MΩ

CLK3

+

OCP –

HICCUP

AND

LATCH-UP

SLOPE

COMP

0.8V

VID3

0.72V

+

CMP3

–

+

EA3

–

CLK3

FREQ

FOLDBACK

0.88V

+

– PWRGD3

OVP

– LATCH-UP

+

CONTROL

LOGIC

AND MOSFET

DRIVER WITH

ANTICROSS

PROTECTION

UVLO3

ACS3

VREG

Q3

DRIVER

VREG

Q4

DRIVER

ZERO

CROSS

CHANNEL 4—BUCK

DUPLICATE

CHANNEL 3

SUPERVISORY

WATCHDOG

DETECTOR

RESET

GENERATOR

DEBOUNCE

0.5V

Figure 2.

PVIN3

BST3

SW3

PGND3

PVIN4

BST4

SW4

PGND4

RSTO

VTH

Data Sheet

Rev. B | Page 4 of 55

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