DA1843JS View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
DA1843JS Datasheet PDF : 64 Pages
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PIN CONFIGURATIONS
80-Lead PQFP
AD1843
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SDO 1
SDFS 2
GNDD 3
VDD 4
TSI 5
TSO 6
GNDD 7
VDD 8
CS 9
BM 10
AUX3R 11
AUX3L 12
AUX2R 13
AUX2L 14
AUX1R 15
AUX1L 16
MICR 17
MICL 18
MIN 19
VCC 20
AD1843
TOP VIEW
(Not to Scale)
60 GNDD
59 XCTL1
58 XCTL0
57 SYNC3
56 SYNC2
55 SYNC1
54 GNDD
53 VDD
52 RESET
51 PWRDWN
50 VDD
49 PDMNFT
48 GNDA
47 HPOUTL
46 HPOUTC
45 HPOUTR
44 VCC
43 SUML
42 SUMR
41 VCC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PIN DESCRIPTION
Serial Interface
Pin Name PQFP
SCLK
79
TQFP
99
SDFS
2
2
SDI
SDO
80
100
1
1
BM
10
12
REV. 0
I/O Description
I/O Serial Clock. SCLK is a bidirectional signal that supplies the clock as an output
to the serial bus when the Bus Master (BM) pin is driven HI and accepts the clock
as an input when the BM pin is driven LO. When the AD1843 is configured in
master mode, the SCLK frequency may be set to either 12.288 MHz or 16.384 MHz
with the SCF bit in Control Register Address 26.
I/O Serial Data Frame Sync. SDFS is a bidirectional signal that supplies the frame
synchronization signal as an output to the serial bus when the Bus Master (BM)
pin is driven HI and accepts the frame synchronization signal as an input when
the BM pin is driven LO.
I
Serial Data Input. SDI is used by peripheral devices such as the host CPU or a
DSP to supply control and playback data information to the AD1843. All control
and playback transfers are 16 bits long, MSB first.
O Serial Data Output. SDO is used to supply status/control register readback and
capture data information to peripheral devices such as the host CPU or a DSP.
All status/control register readback and capture data transfers are 16 bits long,
MSB first. A three-state output driver is used on this pin.
I
Bus Master. When BM is tied HI the AD1843 is the serial bus master. The
AD1843 will then supply the serial clock (SCLK) and the frame sync (SDFS)
signals for the serial bus. No more than one device (AD1843/CPU/DSP) should
be configured as the serial bus master. When BM is tied LO, the AD1843 is con-
figured as a bus slave, and will accept the SCLK and SDFS signals as inputs. The
logic level on this pin must not be changed once RESET is deasserted (driven HI).
–7–
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