MAX4926ELT View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX4926ELT Datasheet PDF : 7 Pages
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Overvoltage Protectors with
External pFET
Pin Description
PIN NAME
FUNCTION
Voltage Input. IN is both the power-supply input and the overvoltage/undervoltage sense input. Bypass IN to
1
IN GND with a 1µF ceramic capacitor as close as possible to the device to enable ±15kV (HBM) ESD protection
on IN.
2
GND Ground
3
FLAG
Fault Indication Open-Drain Output. FLAG deasserts high during undervoltage and overvoltage lockout
conditions. FLAG asserts low during normal operation.
4
GATE
pFET Gate Drive Output. GATE is driven high during a fault condition to turn off the external pFET. When
VUVLO < VIN < VOVLO, GATE is driven low and the external pFET is turned on.
5, 6 N.C. No Connection. Not internally connected. Leave N.C. unconnected.
Functional Diagram
IN
MAX4923–MAX4926
GATE DRIVER
GATE
GND
OVLO AND
CONTROL
UVLO
LOGIC AND
FLAG
DETECTOR
TIMER
VOVLO
VIN
VGATE
tDEB
O.5V
tGON
tDEB
tGOFF
VIN - 0.5V
tFLAG
O.5V
tGON
VUVLO
tGOFF
VIN - 0.5V
tFLAG
3V
VFLAG
Figure 1. Timing Diagram
4 _______________________________________________________________________________________
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