MAX504 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX504

5V, Low-Power, Voltage-Output, Serial 10-Bit DACs

Maxim Integrated 

5V, Low-Power, Voltage-Output

Serial 10-Bit DACs

____________________Pin Description

PIN

MAX504 MAX515

NAME

FUNCTION

1

—

BIPOFF

Bipolar offset/gain

resistor

2

1

DIN

Serial data input

3

—

CLR

Clear. Asynchronously sets

DAC register to all 0s.

4

2

SCLK Serial clock input

5

3

CS

Chip select, active low

6

4

DOUT

Serial data output for

daisy-chaining

7

—

DGND Digital ground

8

5

AGND Analog ground

9

6

REFIN Reference input

Reference output,

10

—

REFOUT 2.048V. Connect to VDD

if not used.

11

—

VSS

Negative power supply

12

7

VOUT DAC output

13

8

VDD

Positive power supply

14

—

RFB Feedback resistor

_______________Detailed Description

General DAC Discussion

The MAX504/MAX515 use an “inverted” R-2R ladder net-

work with a single-supply CMOS op amp to convert 10-bit

digital data to analog voltage levels (see Functional

Diagram). The term “inverted” describes the ladder net-

work because the REFIN pin in current-output DACs is the

summing junction, or virtual ground, of an op amp.

However, such use would result in the output voltage

being the inverse of the reference voltage. The

MAX504/MAX515’s topology makes the output the same

polarity as the reference input.

An internal reset circuit forces the DAC register to reset

to all 0s on power-up. Additionally, a clear (CLR) pin,

when held low, sets the DAC register to all 0s. CLR

operates asynchronously and independently from the

chip select (CS) pin.

Buffer Amplifier

The output buffer is a unity-gain stable, rail-to-rail output,

BiCMOS op amp. Input offset voltage and CMRR are

trimmed to achieve better than 10-bit performance.

Settling time is 25µs to 0.01% of final value. The output is

short-circuit protected and can drive a 2kΩ load with more

than 100pF load capacitance.

CS

tCSH0

SCLK

tDS

DIN

DOUT

tCSS

tCH

tCL

tDH

tDO

tCSW

tCSH1

tCS1

Figure 1. Timing Diagram

8 _______________________________________________________________________________________

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