MAX9425 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX9425

Lowest Jitter Quad PECL-to-ECL Differential Translators

Maxim Integrated 

Lowest Jitter Quad PECL-to-ECL

Differential Translators

IN_

VIHD - VILD

IN_

OUT_

OUT_

tPLH1

VOH - VOL

tPHL1

80%

VOH - VOL

80%

DIFFERENTIAL OUTPUT

OUT_ - OUT_ WAVEFORM

20%

tR

VOH - VOL

Figure 3. IN to OUT Propagation Delay and Transition Timing Diagram

20%

tF

SEL = HIGH

EN = HIGH

CLK

VIHD - VILD

CLK

tH

tS

tH

IN_

VIHD - VILD

IN_

OUT_

tPLH2

OUT_

Figure 4. CLK to OUT Propagation Delay Timing Diagram

The MAX9425/MAX9427 have internal 50Ω series-out-

put termination resistors and 8mA internal pulldown

current sources, removing the need for external termi-

nation. The MAX9424/MAX9426 have open-emitter out-

puts, which require external termination (see the Output

Termination section).

Enable

Setting EN = high and EN = low enables the device.

Alternatively, setting EN = low and EN = high forces the

outputs to a differential low; all changes on CLK, SEL,

and IN_ are ignored.

tPHL2

VIHD - VILD

SEL = LOW

EN = HIGH

Asynchronous Operation

Setting SEL = high and SEL = low enables the four chan-

nels to operate independently. The clock signal is

ignored in this mode. When asynchronous mode is

selected, drive or bias the CLK and CLK inputs. Biasing

the clock inputs properly is shown in Figure 5. This pre-

vents the unused clock inputs from toggling, which elimi-

nates unnecessary switching noise.

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