MCP3204/3208
CS
CLK
DIN
DOUT
tSUCS
tSU
tHD
MSB IN
tHI
tLO
tCSH
tDO
tR
tEN
NULL BIT MSB OUT
tF
tDIS
LSB
FIGURE 1-1: Serial Interface Timing.
Load circuit for tR, tF, tDO
1.4V
DOUT
3K
Test Point
CL = 100pF
DOUT
Load circuit for tDIS and tEN
Test Point
VDD
tDIS Waveform 2
3K
VDD/2
tEN Waveform
100pF
VSS
tDIS Waveform 1
Voltage Waveforms for tR, tF
Voltage Waveforms for tEN
DOUT
tR
VOH
VOL
tF
Voltage Waveforms for tDO
CLK
tDO
DOUT
FIGURE 1-2: Test Circuits.
CS
123
4
CLK
DOUT
B11
tEN
Voltage Waveforms for tDIS
CS
VIH
DOUT
Waveform 1*
TDIS
90%
DOUT
Waveform 2â€
10%
* Waveform 1 is for an output with internal condi-
tions such that the output is high, unless dis-
abled by the output control.
†Waveform 2 is for an output with internal condi-
tions such that the output is low, unless disabled
by the output control.
DS21298B-page 4
Preliminary
© 1999 Microchip Technology Inc.